1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of post-passivation processing for the creation of conductive interconnects.
2. Description of the Prior Art
Improvements in semiconductor device performance are typically obtained by scaling down the geometric dimensions of the Integrated Circuits; this results in a decrease in the cost per die while at the same time some aspects of semiconductor device performance are improved. The metal connections which connect the Integrated Circuit to other circuit or system components become of relative more importance and have, with the further miniaturization of the IC, an increasingly negative impact on the circuit performance. The parasitic capacitance and resistance of the metal interconnections increase, which degrades the chip performance significantly. Of most concern in this respect is the voltage drop along the power and ground buses and the RC delay of the critical signal paths. Attempts to reduce the resistance by using wider metal lines result in higher capacitance of these wires.
To solve this problem, one approach has been to develop low resistance metal (such as copper) for the wires while low-k dielectric materials are used in between signal lines. Current practice is to create metal interconnection networks under a layer of passivation. This approach, however, limits the interconnect network to fine line interconnects and the therewith associated high parasitic capacitance and high line resistivity. The latter two parameters, because of their relatively high values, degrade circuit performance, an effect which becomes even more severe for higher frequency applications and for long interconnect lines that are, for instance, used for clock distribution lines. Also, fine line interconnect metal cannot carry high values of current that is typically needed for ground busses and for power busses.
It has previously been stated that it is of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity. U.S. Pat. No. 6,383,916 to the same assignee as the present invention provides such a method. An analogy can be drawn in this respect whereby the currently (prior art) used fine-line interconnection schemes, which are created under a layer of passivation, are the streets in a city; in the post-passivation interconnection scheme of the above patent, the interconnections that are created above a layer of passivation can be considered the freeways between cities.
FIG. 1 shows a diagram of a silicon substrate on the surface of which has been created a conductive interconnect network. The structure that is shown in FIG. 1 addresses prior art power and ground distribution networks. The various features that have been highlighted in FIG. 1 are the following:                40, a silicon substrate on the surface of which has been created an interconnect network        42, a sample number of semiconductor circuits that have been created in or on the surface of the substrate 40        44, two electrostatic discharge (ESD) circuits created in or on the surface of the substrate 40; one ESD circuit is provided for each pad that is accessible for external connections (pads 52, see below)        46 is a layer of interconnect lines; these interconnect lines are above the surface of substrate 40 and under the layer 48 of passivation and represent a typical application of prior art fine-line interconnects; these fine-line interconnects of layer 46 typically have high resistivity and high parasitic capacitance.        48 is a layer of passivation that is deposited over the surface of the layer 46 of interconnect lines. The passivation layer is the final layer of the IC process in the prior art. The passivation layer is used to protect the underlying devices and fine-line interconnection from damage by mobile ions, moisture, transition metals, and contamination.        50 is a power or ground bus that connects to the circuits 42 via fine-line interconnect lines provided in layer 46; this power or ground bus is typically of wider metal since this power or ground bus carries the accumulated current or ground connection for the devices 42. The power, ground buses are built in the fine line interconnect under the passivation layer. The fine line interconnection can be in one layer or more than one layer of metals.        52 is a power or ground pad that passes through the layer 48 of passivation and that has been connected to the power or ground bus 50.        
From the above the following can be summarized: circuits are created in or on the surface of a silicon substrate, interconnect lines are created for these circuits for further interconnection to external circuitry, the circuits are, on a per I/O pad basis, provided with an ESD circuit; these circuits with their ESD circuit are connected to a power or ground pad that penetrates a layer of passivation. The layer of passivation is the final layer that overlies the created interconnect line structure; the interconnect lines underneath the layer of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistivity and high parasitic capacitance.
Relating to the diagram that is shown in FIG. 1, the following comment applies: ESD circuits are, as is known in the art, provided for the protection of semiconductor circuits against unwanted electrostatic discharge. For this reason, each pad that connects a semiconductor circuit to the external circuits must be provided with an ESD circuit.
FIG. 2 shows a diagram of a prior art configuration that resembles the diagram shown in FIG. 1. The structure that is shown in FIG. 2 however relates to clock and signal distribution networks. FIG. 2 shows in addition (to the previously highlighted aspects of FIG. 1):                45 are two ESD circuits that are provided in or on the surface of the substrate 40; ESD circuits are always required for any external connection to an input/output (I/O) pad.        45′ which are circuits that can be receiver or driver or I/O circuits for input (receiver) or output (driver) or I/O purposes respectively.        54 is a clock, signal, address, or data bus built in the fine line interconnection metal under the passivation layer. The clock, signal, or buses can be in one layer or in more than one layer of fine line interconnect metals.        56 is a clock or signal pad that has been extended through the layer 48 of passivation.        
The same comments apply to the diagram that is shown in FIG. 2 as previously have been made with respect to FIG. 1, with as a summary statement that the layer of passivation is the final layer that overlies the created structure, the interconnect lines underneath the layer of passivation are fine line interconnects and have all the electrical disadvantages of fine line interconnects such as high resistivity and high parasitic capacitance.
Further with respect to FIG. 2 where pads 56 are signal or clock pads:                pads 56 must be connected to ESD and driver/receiver or I/O circuits 45        for signal or clock pads 56, these pads must be connected not only to ESD circuits but also to driver or receiver or I/O circuits, highlighted as circuit 45′ in FIG. 2        after (clock and signal) stimuli have passed through the ESD and driver/receiver or I/O circuits, these stimuli are further routed using, under prior art methods, fine-line interconnect wires. A layer of passivation is deposited over the dielectric layer in which the interconnect network has been created.        
It is therefore of interest to the semiconductor art to provide a method of creating interconnect lines that removes typical limitations that are imposed on the interconnect wires, such as unwanted parasitic capacitances and high interconnect line resistivity. The present invention is related to U.S. Pat. No. 6,303,423, to the same assignee as the present invention.